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64 Mbit SPI Serial Dual I/O Flash
A Microchip Technology Company
SST25VF064C
Data Sheet
Power-Up Specifications
All functionalities and DC specifications are specified for a V DD ramp rate of greater than 1V per 100
ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset is
required. The recommended V DD power-up to RESET# high time should be greater than 100 μs to
ensure a proper reset. See Table 16 and Figures 26 and 27 for more information.
Table 16: Recommended System Power-up Timings
Symbol
T PU-READ1
Parameter
V DD Min to Read Operation
Minimum
100
Units
μs
T PU-WRITE
1
V DD Min to Write Operation
100
μs
T16.0 25036
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T PU-READ
V DD
RESET#
0V
V DD min
V IH
T RECR
CE#
1203 F37.0
Note: See Table 2 on page 6 for T RECR parameter.
Figure 26: Power-Up Reset Diagram
V DD
V DD Max
Chip selection is not allowed.
All commands are rejected by the device.
V DD Min
T PU-READ
T PU-WRITE
Device fully accessible
Time
1392 F26.0
Figure 27: Power-up Timing Diagram
?2011 Silicon Storage Technology, Inc.
31
DS25036A
06/11
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